View M30260F6AGPU5A_7785528.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics.
single-chip 16-bit cmos microcomputer page 1 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m rej03b0071-0051 rev.0.51 jul.25, 2006 1. overview the m16c/26a group (m16c/26a, m16c/26b, m16c/26t) is a single-chip control mcu, fabricated using high-performance silicon gate cmos technology, embedding the m16c/60 series cpu core. the m16c/ 26a group (m16c/26a, m16c/26b, m16c/26t) is housed in 42-pin and 48-pin plastic molded packages. with a 1m byte address space, this mcu combines advanced instruction manipulation capabilities to pro- cess complex instructions by less bytes and execute instructions at higher speed. the m16c/26a group (m16c/26a, m16c/26b, m16c/26t) has a multiplier and dmac adequate for office automation, communi- cation devices and industrial equipment, and other high-speed processing applications. 1.1 applications audio, cameras, office/communications/portable/ equipment, air-conditioning equipment, home appli- ances, etc.
1. overview page 2 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification cpu basic instructions 91 instructions minimun instruction 41.7 ns (f(bclk) = 24mh z (4) , v cc = 4.2 to 5.5 v) (m16c/26b) execution time 50 ns (f(bclk) = 20mh z , v cc = 3.0 to 5.5 v) (m16c/26a, m16c/26b, m16c/26t(t-ver.)) 100 ns (f(bclk) = 10mh z , v cc = 2.7 to 5.5 v) (m16c/26a , m16c/26b) 50 ns (f(bclk) = 20mh z , v cc = 4.2 to 5.5 v -40 to 105 c) (m16c/26t(v-ver.)) 62.5 ns (f(bclk) = 16mh z , v cc = 4.2 to 5.5 v -40 to 125 c) (m16c/26t(v-ver.)) operating mode single-chip mode address space 1 mbyte memory capacity see 1.4 product information peripheral i/o ports 39 i/o pins function multifunction timers timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer serial i/o 2 channels (uart, clock synchronous serial i/o) 1 channel (uart, clock synchronous, i 2 c bus (1) , or iebus (2) ) a/d converter 10 bit a/d converter : 1 circuit, 12 channels dmac 2 channels crc calcuration circuit 1 circuit (crc-ccitt and crc-16) with msb/lsb selectable watchdog timer 15 bits x 1 channel (with prescaler) interrupts 20 internal and 8 external sources, 4 software sources, interrupt priority level: 7 clock generation circuit 4 circuits main clock oscillation circuit(*), sub-clock oscillation circuit(*) on-chip oscillator, pll frequency synthesizer (*)equipped with a built-in feedback resister. oscillation stop detection main clock oscillation stop, re-oscillation detection function voltage detection circuit on-chip (m16c/26a, m16c/26b), not on-chip (m16c/26t) electrical power supply voltage v cc = 4.2 to 5.5 v (f(bclk) = 24 mh z ) (4) (m16c/26b) characteristics v cc = 3.0 to 5.5 v (f(bclk) = 20 mh z ) (m16c/26a, m16c/26b) v cc = 2.7 to 5.5 v (f(bclk) = 10 mh z ) v cc = 3.0 to 5.5 v (m16c/26t(t-ver.)) v cc = 4.2 to 5.5 v (m16c/26t(v-ver.)) power consumption 16 ma (vcc = 5 v, f(bclk) = 20 mhz) 25 a (f(xcin) = 32 khz on ram) 3 a (vcc = 3 v, f(xcin) = 32 khz, in wait mode) 0.7 a (vcc = 3 v, in stop mode) flash memory programming /erasure 2.7 to 5.5 v (m16c/26a, m16c/26b) version voltage 3.0 to 5.5 v (m16c/26t(t-ver.)) 4.2 to 5.5 v (m16c/26t(v-ver.)) programming /erasure 100 times (all area) or 1,000 times (block 0 to 3) endurance / 10,000 times (block a, block b) (3) operating ambient temperature -20 to 85 c / -40 to 85 c (3) (m16c/26a , m16c/26b) -40 to 85 c (m16c/26t(t-ver.)) -40 to 105 c / -40 to 125 c (m16c/26t(v-ver.)) package 48-pin plastic molded qfp notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. iebus is a trademark of nec electronics corporation. 3. see table 1.7 product code for the program and erase endurance, and operating ambient temperature. 4. the pll frequency synthesizer is used to run the m16c/26b at f(bclk) = 24 mhz. table 1.1. m16c/26a group(m16c/26a, m16c/26b, m16c/26t) performance (48-pin package) 1.2 performance outline table 1.1 and 1.2 outline performance overview of the m16c/26a group (m16c/26a, m16c/26b, m16c/ 26t).
1. overview page 3 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 1.2. performance outline of m16c/26a group (m16c/26a, m16c/26b) (42-pin device) item performance cpu basic instructions 91 instructions minimun instruction 41.7 ns (f(bclk) = 24 mhz (4) , vcc = 4.2 to 5.5 v (m16c/26b) execution time 50 ns (f(bclk) = 20 mh z , v cc = 3.0 to 5.5 v) (m16c/26a, m16c/26b) 100 ns (f(bclk) = 10 mh z , v cc = 2.7 to 5.5 v) (m16c/26a, m16c/26b) operation mode single-chip mode address space 1m byte memory capacity see 1.4 product information peripheral port 33 i/o pins function multifunction timer timer a: 16 bits x 5 channels, timer b: 16 bits x 3 channels three-phase motor control timer serial i/o 1 channel (uart, clock synchronous serial i/o) 1 channel (uart, clock synchronous, i 2 c bus (1) , or iebus (2) ) a/d converter 10 bit a/d converter: 1 circuit, 10 channels dmac 2 channels crc calcuration circuit 1 circuits (crc-ccitt and crc-16) with msb/lsb selectable watchdog timer 15 bits x 1 channel (with prescaler) interrupt 18 internal and 8 external sources, 4 software sources, interrupt priority level: 7 clock generation circuit 4 circuits main clock(*), sub-clock(*) on-chip oscillator, pll frequency synthesizer (*)equipped with a built-in feedback resister. oscillation stop detection main clock oscillation stop, re-oscillation detection function voltage detection circuit on-chip electrical supply voltage v cc = 4.2 to 5.5 v (f(bclk) = 24 mh z ) (4) (m16c/26b) characteristics v cc = 3.0 to 5.5 v (f(bclk) = 20 mh z ) (m16c/26a, m16c/26b) v cc = 2.7 to 5.5 v (f(bclk) = 10 mh z ) power consumption 16 ma (vcc = 5 v, f(bclk) = 20 mhz) 25 a (f(xcin) = 32 khz on ram) 3 a (vcc = 3 v, f(xcin) = 32 khz, in wait mode) 0.7 a (vcc = 3 v, in stop mode) flash memory programming/erasure 2.7 to 5.5 v voltage programming/erasure 100 times (all area) or 1,000 times (block 0 to 3) endurance / 10,000 times (block a, block b) (3) operating ambient temperature -20 to 85 c / -40 to 85 c (3) package 42-pin plastic molded ssop notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. iebus is a trademark of nec electronics corporation. 3. see table 1.7 product code for the program and erase endurance, and operating ambient temperature. 4. the pll frequency synthesizer is used to run the m16c/26b at f(bclk) = 24 mhz.
1. overview page 4 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 1.3 block diagram figure 1.1 and 1.2 show block diagrams of the m16c/26a group (m16c/26a, m16c/26b, m16c/26t) 48- pin package and 42-pin package. figure 1.1 block diagram(48-pin package) timer (16-bit) output (timer a): 5channels input (timer b): 3 channels peripheral functions watchdog timer (15 bits) dmac (2 channels) uart or clock synchronous serial i/o (8 bits x 3 channels) clock generation circuit xin-xout xcin-xcout on-chip oscillator pll frequency synthesizer m16c/60 series cpu core port p1 3 port p10 8 memory rom (1) ram (2) notes: 1: rom size depends on the mcu type. 2: ram size depends on the mcu type. r0l r0h r1h r1l r2 r3 sb flg usp isp intb pc multiplier three-phase motor control circuit a0 a1 fb 8 port p6 8 port p7 8 port p8 4 port p9 crc calculation circuit (ccitt, crc-16 ) 10-bit a/d converter 12 channels
1. overview page 5 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 1.2 block diagram( 42-pin package) timer (16-bit) output (timer a): 5channels input (timer b): 3 channels peripheral functions watchdog timer (15 bits) dmac (2 channels) uart or clock synchronous serial i/o (8 bits x 2 channels) clock generation circuit xin-xout xcin-xcout on-chip oscillator pll frequency synthesizer m16c/60 series cpu core port p1 3 port p10 8 memory rom (1) ram (2) notes: 1: rom size depends on the mcu type. 2: ram size depends on the mcu type. r0l r0h r1h r1l r2 r3 sb flg usp isp intb pc multiplier three-phase motor control circuit a0 a1 fb 4 port p6 8 port p7 8 port p8 2 port p9 crc calculation circuit (ccitt, crc-16 ) 10-bit a/d converter 10 channels
1. overview page 6 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 1.4 product list tables 1.3 to 1.6 lists product information, figure 1.3 shows a product numbering system, table 1.7 lists the product code, and figure 1.4 shows the marking. table 1.3 m16c/26a current as of jul., 2006 r e b m u n e p y t m o r y t i c a p a c m a r y t i c a p a c e p y t e g a k c a ps k r a m e re d o c t c u d o r p p g a 3 f 0 6 2 0 3 m) n (k 4 + k 4 2k 1 ) a - q 6 p 8 4 ( a - b k 8 4 0 0 p q l p h s a l f y r o m e m 9 u , 7 u , 5 u , 3 u p g a 6 f 0 6 2 0 3 m) n (k 4 + k 8 4k 2 p g a 8 f 0 6 2 0 3 m) n (k 4 + k 4 6k 2 p f a 3 f 3 6 2 0 3 m) n (k 4 + k 4 2k 1 ) r 2 p 2 4 ( b - a g 2 4 0 0 p s r p9 u , 5 u p f a 6 f 3 6 2 0 3 m) n (k 4 + k 8 4k 2 p f a 8 f 3 6 2 0 3 m) n (k 4 + k 4 6k 2 p g x x x - a 3 m 0 6 2 0 3 m) n (k 4 2k 1 ) a - q 6 p 8 4 ( a - b k 8 4 0 0 p q l p m o r k s a m 5 u , 3 u p g x x x - a 6 m 0 6 2 0 3 m) n (k 8 4k 2 p g x x x - a 8 m 0 6 2 0 3 m) n (k 4 6k 2 p f x x x - a 3 m 3 6 2 0 3 m) n (k 4 2k 1 ) r 2 p 2 4 ( b - a g 2 4 0 0 p s r p5 u p f x x x - a 6 m 3 6 2 0 3 m) n (k 8 4k 2 p f x x x - a 8 m 3 6 2 0 3 m) n (k 4 6k 2 w e n : ) n ( r e b m u n e p y t m o r y t i c a p a c m a r y t i c a p a c e p y t e g a k c a ps k r a m e re d o c t c u d o r p p g b 8 f 0 6 2 0 3 m) d (k 4 + k 4 6k 2) a - q 6 p 8 4 ( a - b k 8 4 0 0 p q l p h s a l f y r o m e m 7 u p f b 8 f 3 6 2 0 3 m) d (k 4 + k 4 6k 2) r 2 p 2 4 ( b - a g 2 4 0 0 p s r p9 u t n e m p o l e v e d r e d n u : ) d ( r e b m u n e p y t m o r y t i c a p a c m a r y t i c a p a c e p y t e g a k c a ps k r a m e re d o c t c u d o r p p g t 3 f 0 6 2 0 3 mk 4 + k 4 2k 1 ) a - q 6 p 8 4 ( a - b k 8 4 0 0 p q l p h s a l f y r o m e m 7 u , 3 u p g t 6 f 0 6 2 0 3 mk 4 + k 8 4k 2 p g t 8 f 0 6 2 0 3 mk 4 + k 4 6k 2 : e t o n . n o i s r e v m o r k s a m n o s l i a t e d r o f . p r o c g o l o n h c e t s a s e n e r t c a t n o c e s a e l p . 1 r e b m u n e p y t m o r y t i c a p a c m a r y t i c a p a c e g a k c a ps k r a m e re d o c t c u d o r p p g v 3 f 0 6 2 0 3 mk 4 + k 4 2k 1 ) a - q 6 p 8 4 ( a - b k 8 4 0 0 p q l p h s a l f y r o m e m 7 u , 3 u p g v 6 f 0 6 2 0 3 mk 4 + k 8 4k 2 p g v 8 f 0 6 2 0 3 mk 4 + k 4 6k 2 : e t o n . n o i s r e v m o r k s a m n o s l i a t e d r o f . p r o c g o l o n h c e t s a s e n e r t c a t n o c e s a e l p . 1 table 1.4 m16c/26b current as of jul., 2006 table 1.5 m16c/26t t-ver. current as of jul., 2006 table 1.6 m16c/26t v-ver. current as of jul., 2006
1. overview page 7 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 1.3 product numbering system package type: gp: plqp0048kb-a (48p6q) (m16c/26a, m16c/26b, m16c/26t) fp: prsp0042ga-b (42p2r) (m16c/26a, m16c/26b) version: a : m16c/26a b : m16c/26b t : m16c/26t t-ver. v : m16c/26t v-ver. rom / ram capacity: 3: (24k+4k) bytes (note 1) / 1k bytes 6: (48k+4k) bytes (note 1) / 2k bytes 8: (64k+4k) bytes (note 1) / 2k bytes note 1: only flash memory version exists in "+4k bytes" memory type: m: mask rom version f: flash memory version type no. m 3 0 2 6 0 m 8 a - xxx g p - u3 m16c/26a group m16c family pin count (the value itself has no specific meaning) product code: see tables 1.7 to 1.10 rom number: rom number is omitted in flash memory version
1. overview page 8 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m t c u d o r p e d o c e g a k c a p m o r l a n r e t n i ) e c a p s m a r g o r p r e s u ( m o r l a n r e t n i ) e c a p s a t a d ( t n e i b m a g n i t a r e p o e r u t a r e p m e t d n a m a r g o r p e s a r e e c n a r u d n e e r u t a r e p m e t e g n a r d n a m a r g o r p e s a r e e c n a r u d n e e r u t a r e p m e t e g n a r 3 u e e r f d a e l 0 0 1 c 0 6 o t 0 0 0 1c 0 6 o t 0 c 5 8 o t 0 4 - 5 u c 5 8 o t 0 2 - 7 u 0 0 0 , 10 0 0 , 0 1 c 5 8 o t 0 4 -c 5 8 o t 0 4 - 9 u c 5 8 o t 0 2 -c 5 8 o t 0 2 - table 1.7 product code (flash memory version) - m16c/26a, m16c/26b table 1.8 product code (mask rom version - m16c/26a) t c u d o r p e d o c e g a k c a p t n e i b m a g n i t a r e p o e r u t a r e p m e t 3 u e e r f d a e l c 0 4 -o tc 5 8 5 uc 0 2 -o tc 5 8 t c u d o r p e d o c e g a k c a p m o r l a n r e t n i ) e c a p s m a r g o r p r e s u ( m o r l a n r e t n i ) e c a p s a t a d ( t n e i b m a g n i t a r e p o e r u t a r e m e t g n i m m a r g o r p e r u s a r e d n a e c n a r u d n e e r u t a r e p m e t e g n a r g n i m m a r g o r p e r u s a r e d n a e c n a r u d n e e r u t a r e p m e t e g n a r 3 u e e r f d a e l 0 0 1 c 0 6 o t c 0 0 0 1 c 5 8 o t c 0 4 -c 5 8 o t c 0 4 - 7 u0 0 0 , 10 0 0 , 0 1 note: 1. the lead contained products, d3, d5, d7, and d9 are put together with u3, u5, u7, and u9 respectively. lead-free products can be mounted by both conventional sn-pb paste and lead-free paste (sn-ag-cu plating). t c u d o r p e d o c e g a k c a p m o r l a n r e t n i ) e c a p s m a r g o r p r e s u ( m o r l a n r e t n i ) e c a p s a t a d ( t n e i b m a g n i t a r e p o e r u t a r e m e t g n i m m a r g o r p e r u s a r e d n a e c n a r u d n e e r u t a r e p m e t e g n a r g n i m m a r g o r p e r u s a r e d n a e c n a r u d n e e r u t a r e p m e t e g n a r 3 u e e r f d a e l 0 0 1 c 0 6 o t c 0 0 0 1 c 5 2 1 o t c 0 4 -c 5 2 1 o t c 0 4 - 7 u0 0 0 , 10 0 0 , 0 1 table 1.9 product code (flash memory version) - m16c/26t t-ver. table 1.10 product code (flash memory version) - m16c/26t v-ver.
1. overview page 9 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 1.4 marking diagram (m16c/26a , m16c/26b) 0260f8a a u3 xxxxx (1) flash memory version, plqp0048kb-a (48p6q), m16c/26a, m16c/26b m30263f8afp a u3 xxxxxxx (2) flash memory version, prsp0042ga-b (42p2r), m16c/26a, m16c/26b 0260m8a 001a u3 xxxxx (3) mask rom version, plqp0048kb-a (48p6q), m16c/26a m30263m8a-001fp a u3 xxxxxxx (4) mask rom version, prsp0042ga-b (42p2r), m16c/26a product name : indicates m30260f8agp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.7 product code ) date code (5 digits) indicates manufacturing management code product name : indicates m30260m8agp rom number, chip version and product code: 001: indicates rom number a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.8 product code ) date code (5 digits) indicates manufacturing management code product name : indicates m30263f8afp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.7 product code ) date code (7 digits) indicates manufacturing management code product name and rom number m30263m8a and fp are indicated of produnct name 001 is indicated of rom number chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.8 product code ) date code (7 digits) indicates manufacturing management code
1. overview page 10 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 0260f8t a u3 xxxxx 0260f8v a u3 xxxxx (1) flash memory version, plqp0048kb-a (48p6q), m16c/26t t-ver. (2) flash memory version, plqp0048kb-a (48p6q), m16c/26t v-ver. product name : indicates m30260f8vgp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.10 product code ) date code (5 digits) indicates manufacturing management code product name : indicates m30260f8tgp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.9 product code ) date code (5 digits) indicates manufacturing management code figure 1.5 marking diagram (m16c/26t)
1. overview page 11 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p9 2 /tb2 in /an 32 p9 1 /tb1 in /an 31 cnv ss p1 7 /int 5 /idu p1 6 /int 4 /idw p1 5 /int 3 /ad trg /idv p10 7 /an 7 /ki 3 p7 0 /txd 2 /ta 0out /sda 2 /cts 1 /rts 1 /cts 0 /clks 1 x out v ss x in p8 5 /nmi/sd v cc p6 7 /txd 1 p6 6 /rxd 1 p6 5 /clk 1 reset p7 1 /rxd 2 /ta0 in /scl 2 /clk 1 p7 2 /clk 2 /ta1 out /v/rxd 1 p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 p7 4 /ta2 out /w p7 5 /ta2 in /w p7 6 /ta3 out p7 7 /ta3 in p8 0 /ta4 out /u p8 1 /ta4 in /u p8 2 /int 0 p8 3 /int 1 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p6 3 /txd 0 p6 2 /rxd 0 p6 1 /clk 0 p6 0 /cts 0 /rts 0 p9 0 /tb0 in /an 30 /clk out p8 7 /x cin p8 6 /x cout p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref av cc p9 3 /an 24 p8 4 /int 2 /zp note. set pacr2 to pacr0 bit in the pacr register to "100 2 " before you input and output it after resetting to each pin. when the pacr register isn't set up, the input and output function of some of the p ins are disabled. package: plqp0048kb-a (48p6q) 1.5 pin assignments figures 1.6 and 1.7 show the pin assignments (top view). figure 1.6 pin assignment for 48-pin package (top view)
1. overview page 12 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 1.11 pin characteristics for 48-pin package n i p . o n l o r t n o c n i p t r o p t p u r r e t n i n i p n i p r e m i tn i p t r a un i p g o l a n a 19 p 2 b t n i 2 3 n a 2 29 p 1 b t n i 1 3 n a 1 39 p 0 b t n i 0 k l c t u o 3 n a 0 4s s v n c 5x n i c 8 p 7 6x t u o c 8 p 6 7t e s e r 8x t u o 9s s v 0 1x n i 1 1c c v 2 18 p 5 i m nd s 3 18 p 4 t n i 2 p z 4 18 p 3 t n i 1 5 18 p 2 t n i 0 6 18 p 1 a t n i 4 u / 7 18 p 0 a t t u o 4 u / 8 17 p 7 a t n i 3 9 17 p 6 a t t u o 3 0 27 p 5 a t n i 2 w / 1 27 p 4 a t t u o 2 w / 2 27 p 3 a t n i 1 v /s t c 2 s t r / 2 t / x d 1 3 27 p 2 a t t u o 1 v /k l c 2 r / x d 1 4 27 p 1 a t n i 0 r x d 2 l c s / 2 k l c / 1 5 27 p 0 a t t u o 0 t x d 2 a d s / 2 s t r / 1 s t c / 1 s t c / 0 s k l c / 1 6 26 p 7 t x d 1 7 26 p 6 r x d 1 8 26 p 5 k l c 1 9 26 p 4 s t r 1 s t c / 1 s t c / 0 s k l c / 1 0 36 p 3 t x d 0 1 36 p 2 r x d 0 2 36 p 1 k l c 0 3 36 p 0 s t r 0 s t c / 0 4 31 p 7 t n i 5 u d i 5 31 p 6 t n i 4 w d i 6 31 p 5 t n i 3 v d id a g r t 7 30 1 p 7 i k 3 n a 7 8 30 1 p 6 i k 2 n a 6 9 30 1 p 5 i k 1 n a 5 0 40 1 p 4 i k 0 n a 4 1 40 1 p 3 n a 3 2 40 1 p 2 n a 2 3 40 1 p 1 n a 1 4 4s s v a 5 40 1 p 0 n a 0 6 4v f e r 7 4c c v a 8 49 p 3 2 n a 4
1. overview page 13 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 reset av ss p10 0 /an 0 v ref x in x out v ss v cc p8 6 /x cout p6 5 /clk 1 p8 3 /int 1 p8 2 /int 0 p8 1 /ta4 in /u p8 0 /ta4 out /u p7 7 /ta3 in p7 6 /ta3 out p7 5 /ta2 in /w p7 4 /ta2 out /w p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p7 0 /txd 2 /sda 2 /ta0 out /cts 1 /rts 1 /cts 0 /clks 1 p7 1 /rxd 2 /scl 2 /ta0 in /clk 1 p7 2 /clk 2 /ta1 out /v/rxd 1 p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 av cc p9 1 /tb1 in /an 31 p9 0 /tb0 in /an 30 /clk out cnv ss p8 7 /x cin p6 6 /rxd 1 p6 7 /txd 1 p8 5 /nmi/sd p8 4 /int 2 /zp p1 7 /int 5 /idu p1 6 /int 4 /idw p1 5 /int 3 /ad trg /idv p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 note. set pacr2 to pacr0 bit in the pacr register to "001 2 " before you input and output it after resetting to each pin. when the pacr register isn't set up, the input and output function of some of the p ins are disabled. package: prsp0042ga-b (42p2r) figure 1.7 pin assignment for 42-pin package (top view)
1. overview page 14 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 1.12 pin characteristics for 42-pin package n i p . o n l o r t n o c n i p t r o p t p u r r e t n i n i p n i p r e m i tn i p t r a un i p g o l a n a 1s s v a 20 1 p 0 n a 0 3v f e r 4v a c c 59 p 1 b t n i 1 3 n a 1 69 p 0 b t n i 0 k l c t u o 3 n a 0 7s s v n c 8x n i c 8 p 7 9x t u o c 8 p 6 0 1t e s e r 1 1x t u o 2 1s s v 3 1x n i 4 1v c c 5 18 p 5 i m nd s 6 18 p 4 t n i 2 p z 7 18 p 3 t n i 1 8 18 p 2 t n i 0 9 18 p 1 a t n i 4 u / 0 28 p 0 a t t u o 4 u / 1 27 p 7 a t n i 3 2 27 p 6 a t t u o 3 3 27 p 5 a t n i 2 w / 4 27 p 4 a t t u o 2 w / 5 27 p 3 a t n i 1 v /s t c 2 s t r / 2 t / x d 1 6 27 p 2 a t t u o 1 v /k l c 2 r / x d 1 7 27 p 1 a t n i 0 r x d 2 l c s / 2 k l c / 1 8 27 p 0 a t t u o 0 t x d 2 a d s / 2 s t r / 1 s t c / 1 s t c / 0 s k l c / 1 9 26 p 7 t x d 1 0 36 p 6 r x d 1 1 36 p 5 k l c 1 2 36 p 4 s t r 1 s t c / 1 s t c / 0 s k l c / 1 3 31 p 7 t n i 5 u d i 4 31 p 6 t n i 4 w d i 5 31 p 5 t n i 3 v d id a g r t 6 30 1 p 7 i k 3 n a 7 7 30 1 p 6 i k 2 n a 6 8 30 1 p 5 i k 1 n a 5 9 30 1 p 4 i k 0 n a 4 0 40 1 p 3 n a 3 1 40 1 p 2 n a 2 2 40 1 p 1 n a 1
1. overview page 15 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 1.6 pin description apply 0v to the vss pin. apply following voltage to the vcc pin. 2.7 to 5.5 v (m16c/26a, m16c/26b), 3.0 to 5.5 v (m16c/26t t-ver.), 4.2 to 5.5 v (m16c/26t v-ver.) supplies power to the a/d converter. connect the av cc pin to v cc and the av ss pin to v ss ___________ the mcu is in a reset state when "l" is applied to the reset pin connect the cnv ss pin to v ss i/o pins for the main clock oscillation circuit. connect a ceramic resonator or crystal oscillator between x in and x out . to apply external clock, apply it to x in and leave x out open. if x in is not used (for external oscillator or external clock), connect x in pin to v cc and leave x out open i/o pins for the sub clock oscillation circuit. connect a crystal oscillator between x cin and x cout outputs the clock having the same frequency as f1, f 8 , f 32 , or f c ______ ________ input pins for the int interrupt. int2 can be used for timer a z-phase function _______ _______ nmi interrupt input pin. nmi cannot be used as i/o port while the three-phase _______ motor control is enabled. apply a stable "h" to nmi after setting it's direction register to "0" when the three-phase motor control is enabled input pins for the key input interrupt i/o pins for the timer a0 to a4 input pins for the timer a0 to a4 input pin for z-phase timer b0 to b1 input pins output pins for the three-phase motor control timer i/o pins for the three-phase motor control timer input pins to control data transmission output pins to control data reception inputs and outputs the transfer clock inputs serial data outputs serial data output pin for transfer clock applies reference voltage to the a/d converter analog input pins for the a/d converter input pin for an external a/d trigger i/o ports for cmos. each port can be programmed for input or output under the control of the direction register. an input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 3-bit units i/o ports for cmos. each port can be programmed for input or output under the control of the direction register. an input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units v cc, v ss av cc av ss ____________ reset cnv ss x in x out x cin x cout clk out ________ ________ int0 to int5 _______ nmi _____ _____ ki 0 to ki 3 ta0 out to ta4 out ta0 in to ta4 in zp tb0 in to tb1 in ___ ___ u, u, v, v, ___ w, w idu, idw, _____ idv, sd _________ _________ cts1 to cts2 _________ _________ rts1 to rts2 clk1 to clk2 rxd1 to rxd2 txd1 to txd2 clks1 v ref an 0 to an 7 an3 0 to an3 1 ___________ ad trg p1 5 to p1 7 p6 4 to p6 7 p7 0 to p7 7 p8 0 to p8 7 p10 0 to p10 7 p9 0 to p9 1 power supply analog power supply reset input cnvss main clock input main clock output sub clock input sub clock output clock output ______ int interrupt input _______ nmi interrupt input key input interrupt timer a timer b three-phase motor control timer output serial i/o reference voltage input a/d converter i/o ports i i i i i o i o o i i i i/o i i i o i/o i o i/o i o o i i i i/o i/o i : input o : output i/o : input and output classification pin name i/o type description table 1.13 pin description (48-pin and 42-pin packages)
1. overview page 16 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m inputs pin to control data transmission output pin to control data reception inputs and outputs the transfer clock inputs serial data outputs serial data timer b2 input pin analog input pins for the a/d converter i/o ports for cmos. each port can be programmed for input or output under the control of the direction register. an input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units _________ cts0 _________ rts0 clk0 rxd0 txd0 tb2in an2 4 an3 2 p6 0 to p6 3 p9 2 to p9 3 serial i/o timer b a/d converter i/o ports i o i/o i o i i i/o classification pin name i/o type description table 1.13 pin description ( 48-pin packages only) (continued) i : input o : output i/o : input and output
2. cpu page 17 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the register bank is comprised of seven registers (r0, r1, r2, r3, a0, a1 and fb) out of 13 registers. there are two sets of register bank. figure 2.1. cpu register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address regis- ter relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 b reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl.
2. cpu page 18 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0. 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0, and are enabled when the i flag is 1. the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0; usp is selected when the u flag is 1. the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write 0. when read, its content is undefined.
3. memory page 19 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r 3. memory figure 3.1 is a memory map of the m16c/26a group (m16c/26a, m16c/26b, m16c/26t). the m16c/26a group provides 1-mbyte address space addresses 00000 16 to fffff 16 . the internal rom is allocated lower address, beginning with address fffff 16 . for example, a 64-kbyte internal rom area is allocated in addresses f0000 16 to fffff 16 . the flash memory version has two sets of 2-kbyte internal rom area, block a and block b, for data space. these blocks are allocated addresses f000 16 to ffff 16 . the fixed interrupt vectors are allocated addresses fffdc 16 to fffff 16 and they store the start address of each interrupt routine. the internal ram is allocated higher addresses, beginning with address 00400 16 . for example, a 1-kbyte internal ram area is allocated in addresses 00400 16 to 007ff 16 . the internal ram is used for temporarily storing data. the area is also used as stacks when subroutines are called or interrupt requests are ac- knowledged. the sfr is allocated addresses 00000 16 to 003ff 16 . the peripheral function control registers are allo- cated here. all blank spaces within sfr location are reserved and cannot be accessed by users. the special page vectors are allocated addresses ffe00 16 to fffdb 16 . they are used for the jmps instruction and jsrs instruction. refer to the renesas publication m16c/60 and m16c/20 series soft- ware manual for details. figure 3.1 memory map 00000 16 xxxxx 16 internal rom (data space) internal rom (program space) sfr internal ram reserved ffe00 16 fffdc 16 fffff 16 note: 1. block a (2 kbytes) and block b (2 kbytes). 2. do not write to the internal rom in mask rom version. undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi 1k bytes 007ff 16 00bff 16 address xxxxx 16 2k bytes size address yyyyy 16 size f4000 16 fa000 16 48k bytes 24k bytes reserved 00400 16 0f000 16 0ffff 16 yyyyy 16 fffff 16 (1) f0000 16 64k bytes internal ram internal rom (2)
3. memory page 20 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r 4. special function register (sfr) table 4.1 sfr information(1) (1) processor mode register 0 pm0 00 16 processor mode register 1 pm1 00001000 2 system clock control register 0 cm0 01001000 2(m16c/26a) 01101000 2(m16c/26t) system clock control register 1 cm1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register prcr xx000000 2 oscillation stop detection register (2) cm2 0x000000 2 watchdog timer start register wdts xx 16 watchdog timer control register wdc 00xxxxxx 2 (3) address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 voltage detection register 1 (4, 5) vcr1 00001000 2 voltage detection register 2 (4, 5) vcr2 00 16 pll control register 0 plc0 0001x010 2 processor mode register 2 pm2 xxx00000 2 low voltage detection interrupt register (5) d4int 00 16 dma0 source pointer sar0 xx 16 xx 16 xx 16 dma0 destination pointer dar0 xx 16 xx 16 xx 16 dma0 transfer counter tcr0 xx 16 xx 16 dma0 control register dm0con 00000x00 2 dma1 source pointer sar1 xx 16 xx 16 xx 16 dma1 destination pointer dar1 xx 16 xx 16 xx 16 dma1 transfer counter tcr1 xx 16 xx 16 dma1 control register dm1con 00000x00 2 notes: 1. the blank spaces are reserved. no access is allowed. 2. bits cm27, cm21, and cm20 do not change at oscillation stop detection reset. 3. the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 by program. the wdc5 bit cannot be u sed in m16c/26t. 4. the vcr1 and vcr2 registers do not change at software reset, watchdog timer reset, and oscillation stop detection reset . 5. registers vcr1, vcr2, and d4int cannot be used in m16c/26t. x : undefined 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register symbol after reset
3. memory page 21 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r note: 1. blank spaces are reserved. no access is allowed. x: undefined 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset int3 interrupt control register int3ic xx00x000 2 int5 interrupt control register int5ic xx00x000 2 int4 interrupt control register int4ic xx00x000 2 uart2 bus collision detection interrupt control register bcnic xxxxx000 2 dma0 interrupt control register dm0ic xxxxx000 2 dma1 interrupt control register dm1ic xxxxx000 2 key input interrupt control register kupic xxxxx000 2 a/d conversion interrupt control register adic xxxxx000 2 uart2 transmit interrupt control register s2tic xxxxx000 2 uart2 receive interrupt control register s2ric xxxxx000 2 uart0 transmit interrupt control register s0tic xxxxx000 2 uart0 receive interrupt control register s0ric xxxxx000 2 uart1 transmit interrupt control register s1tic xxxxx000 2 uart1 receive interrupt control register s1ric xxxxx000 2 timera0 interrupt control register ta0ic xxxxx000 2 timera1 interrupt control register ta1ic xxxxx000 2 timera2 interrupt control register ta2ic xxxxx000 2 timera3 interrupt control register ta3ic xxxxx000 2 timera4 interrupt control register ta4ic xxxxx000 2 timerb0 interrupt control register tb0ic xxxxx000 2 timerb1 interrupt control register tb1ic xxxxx000 2 timerb2 interrupt control register tb2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int1 interrupt control register int1ic xx00x000 2 int2 interrupt control register int2ic xx00x000 2 table 4.2 sfr information(2) (1)
3. memory page 22 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 notes: 1. blank spaces are reserved. no access is allowed. 2. this register is included in the flash memory version. x: undefined address register symbol after reset flash memory control register 4 (note 2) fmr4 01000000 2 flash memory control register 1 (note 2) fmr1 000xxx0x 2 flash memory control register 0 (note 2) fmr0 01 16 three phase protect control register tprc 00 16 on-chip oscillator control register rocr 00000101 2 pin assignment control register pacr 00 16 peripheral clock select register pclkr 00000011 2 nmi digital debounce register nddr ff 16 port1 7 digital debounce register p17ddr ff 16 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ table 4.3 sfr information(3) (1)
3. memory page 23 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r address register symbol after reset 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 note: 1. blank spaces are reserved. no access is allowed. x : undefined timer a1-1 register ta11 xx 16 xx 16 timer a2-1 register ta21 xx 16 xx 16 timer a4-1 register ta41 xx 16 xx 16 three phase pwm control register 0 invc0 00 16 three phase pwm control register 1 invc1 00 16 three phase output buffer register 0 idb0 3f 16 three phase output buffer register 1 idb1 3f 16 dead time timer dtt xx 16 timer b2 interrupt occurrence frequency set counter ictb2 xx 16 position-data-retain function control register pdrf xxxx0000 2 port function control register pfcr 00111111 2 interrupt request cause select register 2 ifsr2a xxxxxxx0 2 interrupt request cause select register ifsr 00 16 uart2 special mode register 4 u2smr4 00 16 uart2 special mode register 3 u2smr3 000x0x0x 2 uart2 special mode register 2 u2smr2 x0000000 2 uart2 special mode register u2smr x0000000 2 uart2 transmit/receive mode register u2mr 00 16 uart2 bit rate register u2brg xx 16 uart2 transmit buffer register u2tb xxxxxxxx 2 xxxxxxxx 2 uart2 transmit/receive control register 0 u2c0 00001000 2 uart2 transmit/receive control register 1 u2c1 00000010 2 uart2 receive buffer register u2rb xxxxxxxx 2 xxxxxxxx 2 table 4.4 sfr information(4) (1)
3. memory page 24 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r table 4.5 sfr information(5) (1) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 note: 1. blank spaces are reserved. no access is allowed. x : undefined address register symbol after reset count start flag tabsr 00 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 one-shot start flag onsf 00 16 trigger select register trgsr 00 16 up-dowm flag udf 00 16 timer a0 register ta0 xx 16 xx 16 timer a1 register ta1 xx 16 xx 16 timer a2 register ta2 xx 16 xx 16 timer a3 register ta3 xx 16 xx 16 timer a4 register ta4 xx 16 xx 16 timer b0 register tb0 xx 16 xx 16 timer b1 register tb1 xx 16 xx 16 timer b2 register tb2 xx 16 xx 16 timer a0 mode register ta0mr 00 16 timer a1 mode register ta1mr 00 16 timer a2 mode register ta2mr 00 16 timer a3 mode register ta3mr 00 16 timer a4 mode register ta4mr 00 16 timer b0 mode register tb0mr 00xx0000 2 timer b1 mode register tb1mr 00xx0000 2 timer b2 mode register tb2mr 00xx0000 2 timer b2 special mode register tb2sc x0000000 2 uart0 transmit/receive mode register u0mr 00 16 uart0 bit rate register u0brg xx 16 uart0 transmit buffer register u0tb xxxxxxxx 2 xxxxxxxx 2 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart0 receive buffer register u0rb xxxxxxxx 2 xxxxxxxx 2 uart1 transmit/receive mode register u1mr 00 16 uart1 bit rate register u1brg xx 16 uart1 transmit buffer register u1tb xxxxxxxx 2 xxxxxxxx 2 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart1 receive buffer register u1rb xxxxxxxx 2 xxxxxxxx 2 uart transmit/receive control register 2 ucon x0000000 2 crc snoop address register crcsar xx 16 00xxxxxx 2 crc mode register crcmr 0xxxxxx0 2 dma0 request cause select register dm0sl 00 16 dma1 request cause select register dm1sl 00 16 crc data register crcd xx 16 xx 16 crc input register crcin xx 16
3. memory page 25 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r table 4.6 sfr information(6) (1) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 note: 1. blank spaces are reserved. no access is allowed. x: undefined register symbol after reset a/d register 0 ad0 xxxxxxxx 2 xxxxxxxx 2 a/d register 1 ad1 xxxxxxxx2 xxxxxxxx 2 a/d register 2 ad2 xxxxxxxx 2 xxxxxxxx 2 a/d register 3 ad3 xxxxxxxx 2 xxxxxxxx 2 a/d register 4 ad4 xxxxxxxx 2 xxxxxxxx 2 a/d register 5 ad5 xxxxxxxx 2 xxxxxxxx 2 a/d register 6 ad6 xxxxxxxx 2 xxxxxxxx 2 a/d register 7 ad7 xxxxxxxx 2 xxxxxxxx 2 a/d trigger control register adtrgcon 00 16 a/d status register 0 adstat0 00000x00 2 a/d control register 2 adcon2 00 16 a/d control register 0 adcon0 00000xxx 2 a/d control register 1 adcon1 00 16 port p1 register p1 xx 16 port p1 direction register pd1 00 16 port p6 register p6 xx 16 port p7 register p7 xx 16 port p6 direction register pd6 00 16 port p7 direction register pd7 00 16 port p8 register p8 xx 16 port p9 register p9 xxxxxxxx 2 port p8 direction register pd8 00 16 port p9 direction register pd9 xxxx0000 2 port p10 register p10 xx 16 port p10 direction register pd10 00 16 pull-up control register 0 pur0 00 16 pull-up control register 1 pur1 00 16 pull-up control register 2 pur2 00 16 port control register pcr 00 16 address
package page 26 ) t 6 2 / c 6 1 m , b 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6 2 f o 6 0 0 2 , 5 2 . l u j 1 5 . 0 . v e r 1 5 0 0 - 1 7 0 0 b 3 0 j e r package b p a 1 h e y 0 .1 5 e 0 . 8 c 0 1 0 l 0 . 3 0 . 5 0 . 7 0 . 05 a 2.4 11. 63 11. 93 12.2 3 a 2 2. 0 e 8 . 2 8 . 4 8 . 6 d 17. 3 17. 5 1 7.7 r e f e r e n ce s y mbo l min n om m ax 0 .2 5 0 . 3 0 . 4 0 .1 3 0 .1 5 0 . 2 p- sso p42- 8 .4x17. 5 - 0 . 80 0.6 g mass[t y p. ] 4 2 p 2 r - e pr s p 00 42 g a- b rene s a s c od e jeita packa g e cod e previous c od e 0 . 65 0 . 95 2. 1 . d imen s i o n s " * 1" and " * 2" note ) d imen s i o n " * 3 " d o e s n ot in c l u de trim o ff s et . y in de x m a r k 1 42 f * 1 * 2 e h e d e b p a c de t a il f a 2 l a 1 t e rmin a l c r oss sec ti on b 1 c 1 b p c 2 . 1 . d imen s i o n s " * 1" and " * 2 " note ) d imen s i o n " * 3 " d o e s n ot in c l u de trim o ff s et . de t a il f l 1 c a l a 1 a 2 * 3 f 4 8 37 36 25 2 4 1 3 1 2 1 * 1 * 2 in de x m a r k y z e z d p e h e h d d e previous c od e jeita packa g e cod e rene s a s c od e pl q p0048kb- a 48p6 q - a mass[t y p. ] 0.2 g p-l q fp48-7x7-0.5 0 1. 0 0 .12 5 0 .2 0 0 .7 5 0 .7 5 0 . 08 0 .2 0 0 .14 5 0 . 09 0 .2 7 0 .2 2 0 .1 7 m a x n om min dimension in millimeters sy mbol r e f e r e n ce 7.1 7. 0 6 . 9 d 7.1 7. 0 6 . 9 e a 9 . 2 9 . 0 8 . 8 8 . 8 1 .7 0 . 2 0 . 1 0 0 . 65 0 . 5 0 . 35 l x 8 0 c 0 . 5 e 0.1 0 y h d e a 1 p b 1 c 1 z d z e l 1
revision history m16c/26a group (m16c/26a, m16c/26b, m16c/26t) shortsheet rev. date description page summary a-1 0.51 07/25/06 - first edition
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 6. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .6.0

▲Up To Search▲

Price & Availability of M30260F6AGPU5A

	To Download M30260F6AGPU5A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .